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MC14022B Octal Counter
The MC14022B is a four-stage Johnson octal counter with built-in code converter. High-speed operation and spike-free outputs are obtained by use of a Johnson octal counter design. The eight decoded outputs are normally low, and go high only at their appropriate octal time period. The output changes occur on the positive-going edge of the clock pulse. This part can be used in frequency division applications as well as octal counter or octal decode display applications.
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* * * * * * *
Fully Static Operation DC Clock Input Circuit Allows Slow Rise Times Carry Out Output for Cascading Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range Pin-for-Pin Replacement for CD4022B Triple Diode Protection on All Inputs
MARKING DIAGRAMS
16 PDIP-16 P SUFFIX CASE 648 MC14022BCP AWLYYWW 1 16 SOIC-16 D SUFFIX CASE 751B 1 14022B AWLYWW
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value - 0.5 to +18.0 - 0.5 to VDD + 0.5 10 500 - 55 to +125 - 65 to +150 260 Unit V V mA mW C C C A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week
ORDERING INFORMATION
Device MC14022BCP MC14022BD MC14022BDR2 Package PDIP-16 SOIC-16 SOIC-16 Shipping 2000/Box 2400/Box 2500/Tape & Reel
1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
v
v
(c) Semiconductor Components Industries, LLC, 2000
1
March, 2000 - Rev. 3
Publication Order Number: MC14022B/D
MC14022B
PIN ASSIGNMENT
Q1 Q0 Q2 Q5 Q6 NC Q3 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD R C CE Cout Q4 Q7 NC
NC = NO CONNECTION
BLOCK DIAGRAM
CLOCK 14 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Cout 2 1 3 7 11 4 5 10 12
FUNCTIONAL TRUTH TABLE (Positive Logic)
Clock 0 X Clock Enable X 1 0 X Reset 0 0 0 0 0 0 1 Output=n n n n+1 n n+1 n Q0
CLOCK ENABLE
13
RESET
15
VDD = PIN 16 VSS = PIN 8 NC = PIN 6, 9
1 X X
X
X = Don't Care. If n < 4 Carry = 1, Otherwise = 0.
LOGIC DIAGRAM
11 Q4 1 Q1 5 Q6 7 Q3
CLOCK 14 13 CLOCK ENABLE 15 RESET VSS VDD
CQ C D RQ CQ C D RQ CQ C D RQ CQ C D RQ
CARRY 12
Q0 2 4
Q5 3
Q2 10
Q7
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3. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 4. The formulas given are for the typical characteristics only at 25_C. 5. To calculate total supply current at loads other than 50 pF:
where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.00125.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Total Supply Current (4.) (5.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)
Quiescent Current (Per Package)
Input Capacitance (Vin = 0)
Input Current
Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)
Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)
Output Voltage Vin = VDD or 0
(VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)
(VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)
Vin = 0 or VDD
Characteristic
IT(CL) = IT(50 pF) + (CL - 50) Vfk
"1" Level
"1" Level
"0" Level
Source
Sink
Symbol
VOH
VOL
IOH
VIH
IDD
Cin
IOL
VIL
Iin
IT
VDD Vdc
5.0 10 15
5.0 10 15
5.0 10 15
5.0 5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
15
--
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- 3.0 - 0.64 - 1.6 - 4.2 4.95 9.95 14.95 0.64 1.6 4.2 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- --
MC14022B
- 55_C
3 0.1 0.05 0.05 0.05 Max 5.0 10 20 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 4.95 9.95 14.95 0.51 1.3 3.4 Min IT = (0.28 A/kHz)f + IDD IT = (0.56 A/kHz)f + IDD IT = (0.85 A/kHz)f + IDD 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- 0.00001 Typ (3.) - 4.2 - 0.88 - 2.25 - 8.8 25_C 0.005 0.010 0.015 0.88 2.25 8.8 2.75 5.50 8.25 2.25 4.50 6.75 5.0 5.0 10 15 0 0 0 0.1 0.05 0.05 0.05 Max 5.0 10 20 7.5 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 4.95 9.95 14.95 0.36 0.9 2.4 Min 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- 125_C 1.0 0.05 0.05 0.05 Max 150 300 600 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- mAdc mAdc Adc Adc Adc Unit Vdc Vdc Vdc Vdc pF
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6. The formulas given are for the typical characteristics only at 25_C. 7. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)
Clock Enable Removal Time
Clock Enable Setup Time
Clock Input Rise and Fall Time
Reset Removal Time
Reset Pulse Width
Clock Frequency
Clock Pulse Width
Turn-Off Delay Time Reset to Cout tPLH = (1.7 ns/pF) CL + 315 ns tPLH = (0.66 ns/pF) CL + 142 ns tPLH = (0.5 ns/pF) CL + 100 ns
Propagation Delay Time Clock to Decode Output tPLH, tPHL = (1.7 ns/pF) CL + 415 ns tPLH, tPHL = (0.66 ns/pF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 150 ns
Propagation Delay Time Clock to Cout tPLH, tPHL = (1.7 ns/pF) CL + 315 ns tPLH, tPHL = (0.66 ns/pF) CL + 142 ns tPLH, tPHL = (0.5 ns/pF) CL + 100 ns
Propagation Delay Time Reset to Decode Output tPLH, tPHL = (1.7 ns/pF) CL + 415 ns tPLH, tPHL = (0.66 ns/pF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 150 ns
Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
Characteristic
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tTLH, tTHL Symbol
MC14022B
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tTLH, tTHL
tPLH
trem
trem
tWH
tWH
tsu
fcl
4 VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min 420 200 140 350 150 115 750 275 210 500 250 190 250 100 75 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- No Limit Typ (7.) 260 100 70 175 75 52 375 135 105 250 125 95 125 50 35 400 175 125 275 125 95 400 175 125 500 230 175 100 50 40 5.0 12 16 1000 460 350 1000 460 350 Max 800 350 250 800 350 250 200 100 80 2.0 5.0 6.7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MHz Unit ns ns ns ns ns ns ns ns ns ns --
MC14022B
VDD Vout Output Sink Drive Output Source Drive Clock to desired Output (S1 to B) S1 to A - VDD Vout - VDD
VSS VDD A
VSS
S1
B
CLOCK Q0 ENABLE Q1 Q2 Q3 RESET Q4 Q5 Q6 Q7 CLOCK C out VSS
Outputs ID Carry VGS = EXTERNAL POWER SUPPLY VDS =
(S1 to A) Clock to Q5 thru Q7 (S1 to B) VDD Vout
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
VDD 500 F ID 0.01 F CERAMIC
CLOCK ENABLE RESET PULSE GENERATOR fc
CLOCK
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Cout
VSS
CL
CL
CL
CL
CL
CL
CL
CL
CL
Figure 2. Typical Power Dissipation Test Circuit
APPLICATIONS INFORMATION Figure 3 shows a technique for extending the number of decoded output states for the MC14022B. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay).
C
R MC14022B
C
R MC14022B
C
R MC14022B
CE Q0 Q1 * * * Q6 Q7
CE Q0 Q1 * * * Q6 Q7
CE Q1 * * * Q6 Q7 6 DECODED OUTPUTS
7 DECODED OUTPUTS
6 DECODED OUTPUTS
CLOCK FIRST STAGE INTERMEDIATE STAGES LAST STAGE
Figure 3. Counter Expansion http://onsemi.com
5
MC14022B
tWH CLOCK CLOCK ENABLE trem RESET Q0 tPHL tPLH Q1 tPHL 90% tPLH tPHL tTLH 50% 10% tPLH 50% tTHL tPLH trel tsu 20 ns 10% 20 ns 20 ns tWL 90% VDD 50% VSS VDD VSS VDD VSS VOH VOL VOH VOL VOH Q2 tPLH tPHL tTLH VOL VOH Q3 tPLH Q4 tPLH tPHL tPHL tTLH VOL VOH tTLH VOL tPHL VOH
20 ns
20 ns
Q5
tTLH
tPLH tPLH
tTHL
tPHL
tTLH
tTHL VOH VOL
VOL
Q6 tPHL tTLH tPHL tTLH tTHL tPLH
VOH VOL VOH tTHL VOL
Q7 Cout tPHL
Figure 4. AC Measurement Definition and Functional Waveforms
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MC14022B
PACKAGE DIMENSIONS
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
-A-
SOIC-16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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MC14022B
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O
LE Q1 E HE
1 8
16
9
M_ L DETAIL P
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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MC14022B/D

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